In my past, I have gathered my hardware knowledge in a range of categories: Research in general purpose compute architectures – machine vision technology – 4G/5G radio frequency technology – mixed signal interposer technology.
I participated in the whole development flow from concept, implementation, verification to testing on FPGA, tapeout and bringup of silicon.
Digital Design Services I Provide
I have relevant experience in all listed items.
- System Design
- Data capturing
- Data processing & transportation
- Data output
- Design for ASIC or FPGA
- Design concept and RTL implementation from scratch
- Extending, refactoring design
- Low power design, low latency design, high performance design
- Move no data, low clock frequency, few caches, gate everything
- Optimizing for area, power or performance
- Clock gating, power gating, data path gating
- Static timing analysis (only experienced in FPGA)
- IP integration
- Mixed-Signal controller design
- Design for data path and control path
- toplevel wiring & clocking
- dynamic reconfiguration
- Design under microarchitecture considerations for
- CPUs, DSPs, fully customized accelerators
- Superscalar or (VL-)VLIW architectures
- Modifications of instruction set
- Multicycle pipeline design
- Exception handling
- Transparent accelerator design
- Protocols & Bus interface integration
- APB
- AXI-Bus
- I2C-Bus
- Fully customized, fault tolerant, highspeed, low latency protocol for board-to-board communication using Xilinx-high-speed transceivers.
Design Verification Services I Provide
I have relevant experience in all listed items.
- System Verification
- Testing if output pins show expected behavior for corresponding input vector
- Bus infrastructure verification
- Network-on-chip verification
- Deadlock checks
- Mixed Signal considerations
- ASIC Verification
- Bringup support
- Clock gating verification
- Power islands verification
- Microarchitecture verfification
- Cache testing
- Multicore mirroring
- Multicore cross checks
- heterogeneous architecture tests CPU to DSP
- Verification of CPU cores or DSP cores
- Blocklevel Verification
- FPGA Verification
- Design synthesis and testing on FPGA
- Reading internal registers with ChipScope
- Using other external indicators like LEDs
- General
- Modifying or designing new tests
- Extending Coverage
- Increasing coverage by designing tests to cover untested features of architecture
- Verification Types
- Full custom testbench, vendor given testbench, UVM
- Verification with modelling Writing C-model from algorithm specification
- Cycle and register accurate modelling
- Transaction accurate modelling
- Power Aware Simulation
- blocklevel or toplevel simulations
- RTL-simulation, netlist simulation, gatelevel simulation, power aware simulation with power islands
- coverage report simulation
- Switching Activity power budget verification
- Stimuli Generation Methods
- Constraint Random Functional Verification
- Constraint random stimulus vector generation
- Design from scratch
- Extending existing coverage
- Extending for new features
- With Modelling
- Directed Functional Verification
- Mathematical Modelling
- Stimuli by highlevel C-driven tests
- Stimuli by Assembler tests (parallel assembler where needed)
- Simulations of every level: RTL-, gate- and power-aware-gate-level.; Studied and modified existing testcases to meet new design. Designed new testcases in C to test new architectural features.
- Constraint Random Functional Verification
Familiar Languages & Tools
- Languages
- Verilog / SystemVerilog (with UVM)
- TCL
- VHDL
- SystemC
- Python, Perl
- C / C++
- Shell scripting
- Gnu make
- Assembler
- Tools
- General
- Very familiar with Linux
- Git, SVN, Clearcase
- Linting scripts
- Valgrind, gdb
- Bugzilla, Jira
- Synopsys
- DVE, VCS, Verdi, Design Compiler, DesignWare IP
- Cadence
- Simvision, Xcelium Simulator
- Xilinx
- Vivado, Vivado HLS, ISE, Platform Studio, SDK, iSim
- Mentor
- ModelSim
- Intel/Altera
- Quartus
- General